The present invention relates to hard mask patterns of a semiconductor device and a method for forming the same, and more particularly, to hard mask patterns of a semiconductor device, which can be used when implementing an etching process for defining a plurality of contact holes to be arranged in the shape of a matrix, and a method for forming the same.
A plurality of semiconductor elements such as transistors are formed in a semiconductor substrate, and metal lines are formed to electrically connect the semiconductor elements. The metal lines and the junction areas (for example, the source or drain areas of the transistors) of the semiconductor substrate are electrically connected by contact plugs.
In the case of a DRAM (dynamic random access memory) device, transistors and storage node contact plugs are formed in a semiconductor substrate. Contact holes are defined in an interlayer dielectric before forming the contact plugs. DRAM devices are categorized depending upon the arrangement of transistors and capacitors. In a 4F4 DRAM device, storage node contact plugs are arranged in the shape of a matrix in a cell region. After transistors are formed, an interlayer dielectric is formed, and a plurality of contact holes are defined in the interlayer dielectric in a cell region and are arranged in the shape of a matrix. As the integration level of a semiconductor device increases, the arrangement of the contact holes in the 4F4 DRAM device has a pitch less than the resolution limit of exposure equipment. Thus, when forming a photoresist pattern for defining the areas in which contact holes are to be defined, a photolithographic process must be implemented twice for a photoresist layer. As a result, processing costs increase. Furthermore, it is difficult to decrease a resolution index (k1) below 0.20.